
DS26503 T1/E1/J1 BITS Element
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Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only)
FROM RX
LIU
TO TX
LIU
CLOCK
+ DATA
- DATA
CLOCK
+ DATA
- DATA
TO RX
FRAMER
FROM TX
FORMATTER
RCLK
+ DATA
- DATA
TX CLOCK
+ DATA
- DATA
REMOTE
LOOPBACK
(LBCR.4)
LOCAL
LOOPBACK
(LBCR.3)
JITTER
ATTENUATOR
ENABLED AND
IN RX PATH
JITTER
ATTENUATOR
ENABLED AND
IN TX PATH
Figure 3-3. Transmit PLL Clock Mux Diagram
TX PLL
OUTPUT = 1.544MHz,
2.048MHz, 6.312MHz
JA CLOCK
RECOVERED CLOCK
PLL_OUT PIN
TX CLOCK
TCLK PIN
TPCR.2
TPCR.0
(TCSS0)
TPCR.1
(TCSS1)
TPCR.5
IN
SEL
OUT
SEL
TPCR.3
TPCR.4
TPCR.6
TPCR.7
(HARDWARE MODE PIN NAME)